▲Show HN: We built an 8-bit CPU as 2nd year EE students(github.com)
60 points by CorRupT9 2 days ago | 10 comments
▲gabrielsroka 6 hours ago
Ben Eater's SAP came from "Digital Computer Electronics" by Albert Paul Malvino and Jerald A. Brown

https://en.wikipedia.org/wiki/Simple-As-Possible_computer

▲dyauspitr 3 hours ago
Yep this is how I built my SAP 20 years ago.
▲jdw64 3 hours ago
I did something similar for a school capstone project. It brings back memories. Writing Verilog, working with FPGAs, that sort of thing. But this goes even further and actually gets into hardwired implementation, which is really impressive. Actually, using if else statements just creates MUXes, so you don't have fanout issues to worry about. But for something like this, you would have to handle timing calculations for rising and falling edges. It is really remarkable.
▲peterus 5 hours ago
Awesome project, re fpga implementation one option you might want to explore are used Bitcoin miner control boards if you want the best logic units/$ ratio. I've used the EBAZ4205 (zynq 7010) control boards with a cheap/generic FT2232HL dev board and it works great. Of course it's a bit more of a pain compared to a regular dev board
▲wildzzz 4 hours ago
If they are taking digital design classes, they'll probably be given something like a DE0-Nano that can run this just fine.
▲osigurdson 4 hours ago
A 2nd year project back in the day was to build a 4 bit CPU on a breadboard. We had the advantage of having an ALU IC but was still quite tough to get working!
▲dreamcompiler 4 hours ago
"This makes the machine transparent in a way that microcode-based designs cannot be."

Every output bit m of microcode can be equivalently expressed as a logic function of n inputs where the microcode has n incoming address lines. This no less transparent than pure logic if you know the contents of the microcode. Microcode is often preferred because changing it is much easier than changing a bunch of gate logic. IMHO factoring your design into registers vs. control signals and putting the control signals into microcode makes the design more transparent than having a giant sea of gates.

▲momoraul 5 hours ago
the rom-to-ram bootstrap is a nice touch. after it hands over, what stops the bootloader from writing to I-SRAM again? a mode flag in the control matrix?
▲hypfer 2 hours ago
Neat!

Now do it the other way round and make the 8 bit cpus become a 2nd year EE student.

▲HerbManic 5 hours ago
With all the talk about developers being lazy and younger folk not understanding the technology they use, it is always great to see examples of core foundational work still being done. Makes the rest of that talk feel like fear mongering.
▲wl 3 hours ago
I did an undergraduate electrical engineering degree some years ago. Building a CPU much like this one was the final project in our second digital design class. The difference here from the usual approach, as they point out, is that this is a gate-by-gate design you could assemble out of 74-series logic gates on a breadboard rather than the more common Verilog/VHDL designs that target FPGAs. Definitely a more tedious, time consuming approach, but I'm not convinced it's more conceptually difficult. By the time you're building a CPU, you've probably already built the component parts like the adders out of pure logic gates, anyway.

Not to say that this is easy, but I think you'd find that a whole lot more people are doing this kind of thing than you might think.

▲andrewvu0203 1 hour ago
[flagged]
▲roshiya 1 day ago
[dead]